1. Field of the Invention
The present invention relates to memory arrays for usage in circuits including microprocessors. More specifically, the invention relates to the recovery of bit lines in a memory array after a write operation.
2. Description of the Related Art
Today's computer systems and other electronic devices utilize memory arrays to store data. Some examples of memory arrays are data caches and instruction caches on an integrated processor chip such as the K6 processor manufactured by ADVANCED MICRO DEVICES, INC. of Sunnyvale, Calif. Most memory arrays utilize a two bus or bit lines per bit arrangement to write and read data stored in a memory cell electrically coupled to the bit line pair. Typically, to write a logical one or logical zero to a memory cell, one of the two bit lines is driven to a low voltage level during the write operation. The specific bit line of the two bit lines driven low during a write operation determines whether a logical one or logical zero is stored in the memory cell during the write operation.
To read a memory cell to determine whether a logical one or logical zero is stored, a word line electrically coupled to each memory cell in a row of cells is activated or driven high to cause one of the bit lines to dip in voltage. Which bit line of the pair that dips in voltage depends on whether a logical one or a logical zero is stored in the memory cell. Each bit line of a bit line pair is connected to an input of a differential sensing amplifier. During a memory read, the voltage level of the output of the sensing amplifier indicates whether a logical one or logical zero is stored in the memory cell.
After a write to the memory cell is complete, the voltage level of the written bit line (the bit line driven low during the write operation) needs to be recovered before the next read or write operation. To decrease the recovery time or propagation delay after a write operation, a recovery circuit can be implemented in each column circuit of the array to recover the bit line pair after a write operation. Typically, these recovery circuits are activated by a global recovery signal which activates all of the recovery circuits in a memory array after a write operation regardless of whether a particular column circuit was involved in a write operation.
One problem with indiscriminately activating the recovery circuits of a memory array is that power is dissipated in activating the recovery circuits of a column circuit not selected for a write operation. With the power consumption and heat dissipation requirements of today's processors, it would be desirable to reduce the power consumed and heat produced by a memory array due to a write operation.
What is needed is a memory array that consumes less power and produces less heat due to a write operation.